1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, more particularly, to a technique for forming memory cell contacts of a semiconductor memory device such as a DRAM (dynamic random access memory) and a pseudo SRAM (static random access memory).
2. Description of the Related Art
Recently, dimension reduction has been advanced in memory devices, such as DRAMs, which include one transistor and one capacitor in each memory cell, and pseudo SRAMs, which have the same cell structure as that of DRAMs. The dimension reduction provides an increased memory capacity while reducing the chip cost due to the yield increase.
The dimension reduction in the semiconductor memory cell is, however, undesirably accompanied by the difficulty in providing a clearance between the gate electrode and the cell contact within each memory cell. One known approach to address this problem is to use a self-align contact technique in which the cell contact is self-aligned with respect to the gate electrode with the cell contact size adjusted to be equal to the distance between adjacent gate electrodes.
The following is prior art documents found through the Applicant's search related to the present invention:    Japanese Laid Open Patent Application No. JP-A 2000-269458,    Japanese Laid Open Patent Application No. JP-A 2007-067250,    Japanese Laid Open Patent Application No. 1993-343669, and    Japanese Laid Open Patent Application No. 1994-021089.
One issue in next generation semiconductor devices in which the gate length is reduced below the quarter micron order is production of minute particles during the gate electrode formation. Minute particles may work as etching masks and cause production of skirt-like etching residuals adjacent to the gate electrodes. The skirt-like etching residuals may be directly contacted to the cell contacts formed thereafter, causing short-circuiting between a bitline and a gate electrode or between a capacity electrode and the gate electrode. This may undesirably lower the production yield. It is also a problem that the defects resulting from the minute particles necessitate performing product screening for detecting initial defects with severe conditions.
The suppression of the above described phenomenon is of importance to achieve a high yield in a customer sub-constructor's production process and to maintain a high reliability in a market, especially in a case of the KGD (Known Good Die) business based on the SIP (System In Package) and the MCM (Multi Chip Module). One currently-used approach to address this problem is optimization of the etching conditions for reducing minute particles; however, further advance is desired to address the problem of minute particles, since the detection by an automatic defect detecting machine may face limitations with the further dimension reduction.
In the following, a detailed description is given of the problem of the minute particles, referring to FIGS. 1A to 1H. At first, isolation oxide films 102 are formed within the surface portion of a P-type silicon substrate 101 by using a trench isolation technique. A gate oxide film 103 is then formed in active regions isolated by the isolation oxide films 102. This is followed by sequentially depositing an N+-doped silicon film 104, a tungsten silicide film 105, and a CVD oxide film 106 to cover the P-type silicon substrate 101 as shown in FIG. 1A.
The CVD oxide film 106 is then etched with a photoresist pattern used as a mask to form mask oxide films 107 as shown in FIG. 1B. Furthermore, cell gate electrodes 108 are formed by subsequently etching the tungsten silicide film 105 and the N+-doped silicon film 104 with the mask oxide films 107 used as a mask. It should be noted that minute particles may be produced in the etching process of the N+-doped silicon film 104, and the minute particles may work as a mask to locally produce residuals 109 from the N+-doped silicon film 104.
This is followed by forming N-type diffusion layers 110 by an ion implantation technique with the cell gate electrodes 108 used as a mask as shown in FIG. 1C. After a first nitride film 111 is then formed to cover the entire surface, an interlayer dielectric 112 is formed and then flattened by a CMP (chemical mechanical polishing) technique, as shown in FIG. 1D. Subsequently, cell contact holes 113 are formed by etching the interlayer dielectric 112 with a photoresist pattern used as a mask and the first nitride film 111 used as a stopper, as shown in FIG. 1E. Furthermore, the first nitride film 111 is etched back to expose the P-type silicon substrate 101 in the cell contact holes 113. This process also results in the formation of sidewalls 114 from the first nitride film 111 on the side faces of the cell gate electrodes 108. At this moment, portions of the residuals 109 are exposed because of the difference in the etching rate between the first nitride film 111 and the residuals 109, which are formed of N+-doped silicon, as shown in FIG. 1F.
This is followed by filling the cell contact holes 113 with N+-doped silicon contacts 115 through depositing an N+-doped silicon film on the entire surface and performing an etch-back process. This may result in forming a short-circuiting portion 116 which undesirably short-circuits a cell gate electrode 108 and an N+-doped silicon contact 115, because the residuals 109 are partially exposed and the exposed portions directly contacts to the N+-doped silicon contact 115 as shown in FIG. 1G. Subsequently, capacitor contacts 117, capacitor electrodes 118, capacitor dielectrics 119, and capacitor plates 120 are formed after forming an interlayer dielectric film. This is followed by forming bitline contacts 121 and bit lines 122 after forming another interlayer dielectric film so that the bit line contacts 121 are connected to the cell contacts 113. As a result, DRAM memory cells, which each include one transistor and one capacitor, are completely manufactured as shown in FIG. 1H.
The above-described manufacture process, however, suffers from a problem of short-circuiting between the bitlines 122 and the gate electrodes 108 and/or between the capacitor electrodes 118 and the cell gate electrodes 108, because the cell gate electrodes 108 may be electrically connected to the contacts (each composed of a capacitor contact 117 and a bitline contact 121) through the residuals 109, as described above.